When a computer system interfaces with a Double Data Rate source synchronous memory, a DDR controller typically manages the flow of data between the host device for the DDR controller and the DDR memory device(s). The DDR protocol specifies the transfer of data on both the rising and falling edges of the data bus strobe (typically referred to as DQS) signals. The DDR controller typically interfaces with the DDR memory device using a Physical (PHY) interface that converts digital signals and commands from the DDR controller logic into waveforms that the DDR memory can interpret.
As the data rates between the DDR memory and DDR controller increase, it becomes increasingly important to test the robustness of the functionality and timing of the DDR PHY interface. Thus, a number of techniques have been proposed or suggested for the testing of bit errors due to functional and timing issues related to the DDR PHY interface. Existing techniques typically employ external test equipment to exercise and implement a bit error test of the DDR PHY interface. The time required to setup such external test equipment, however, is significant and a relatively large number of pins are typically required to implement the testing. In addition, existing bit error testing techniques typically require that the DDR memory is connected to the DDR controller during testing, via the DDR PHY interface. Furthermore, existing external bit error testing techniques do not permit the DDR controller and the DDR memory to be bypassed to permit proper testing of the PHY interface in isolation.
A need therefor exists for improved methods and apparatus for functional/timing bit error testing of the DDR PHY interface of the overall DDR memory system. A further need exists for improved techniques for bit error testing and training of the DDR PHY interface that do not require the presence of the DDR memory or the DDR memory controller.